1. Field of the Invention
The present invention relates to a semiconductor device including an I/O cell functioning as an external terminal.
2. Description of the Related Art
In general, a semiconductor device includes an I/O cell serving as an input/output unit for connecting between an internal circuit and an external device or the like. The I/O cell has an electrode pad connected to a bonding wire or formed with a bump; thus, the semiconductor device is electrically connected to the external device or the like. In an inspection of the semiconductor device, a probe is brought into contact with the electrode pad, so that the semiconductor device is electrically connected to a tester.
Description will be given of a structure of an I/O cell in a conventional semiconductor device with reference to FIGS. 9A, 9B, 10 and 11.
FIG. 9A is a plan view illustrating a conventional semiconductor device. FIG. 9B is an enlarged view mainly illustrating a region of an I/O cell in the conventional semiconductor device. Specifically, FIG. 9B is an enlarged view of an I/O region illustrated in FIG. 9A. FIG. 10 is a sectional view illustrating a portion near the I/O region in the conventional semiconductor device, taken along a line A-A in FIGS. 9A and 9B. Also, FIG. 10 schematically illustrates a state of an electrode pad in probing. FIG. 11 is a sectional view illustrating an electrode pad formed with a bump in the conventional semiconductor device.
The semiconductor device includes an active region 10 having an internal circuit formed thereon and an I/O region having an I/O cell 11 formed thereon. The I/O cell 11 serves as an input/output unit connected to the internal circuit.
As illustrated in FIGS. 9A, 9B and 10, the conventional I/O cell 11 leads signals, power and the like from the internal circuit formed on the active region 10 to a pad metal 12 formed by a Cu wire at an uppermost layer of the I/O region formed by a plurality of layered Cu wires (this structure is not illustrated in the figures) and is connected, through a via 15, to an Al electrode pad 14 exposed from a SiN film 13 (not illustrated in FIGS. 9A and 9B) formed on a surface of the semiconductor device. Herein, the pad metal 12 has a shape almost equal to that of the electrode pad 14. In many cases, each of the pad metal 12 and the electrode pad 14 has a size in a range from 50 μm×80 μm to 70 μm×100 μm, and the Al electrode pad 14 has a thickness in a range from 450 μm to 2 μm.
When the semiconductor device is formed of a package such as a QFP or a BGA, as illustrated in FIG. 11, a bump 18, a solder ball or the like is formed on a region other than a probe region 16 of the electrode pad 14.
In an inspection, a probe 17 connected to a tester is brought into contact with the probe region 16 of the electrode pad 14. Upon contact of the probe 17, the electrode pad 14 is perforated along a traveling direction of the probe 17. Herein, the electrode pad 14 is perforated such that the pad metal 12 is exposed from the hole, so that the probe 17 may be directly connected to the electrode pad 14.
In terms of a problem of processing precision, however, surface flatness tends to deteriorate upon forming a pattern with a large area. In the structure of the conventional I/O cell, the electrode pad 14 has a minimum area required to perform probing; therefore, the pad metal 12 having a shape almost equal to that of the electrode pad 14 is enlarged in area. Thus, irregularities are formed on a surface of the pad metal 12 and surface flatness deteriorates. Consequently, stress concentration at the irregularities on the surface of the pad metal 12 causes cracking of the pad metal 12 upon contact of the probe 17. In some cases, such cracking occurs at an interlayer film. Consequently, the following problem arises: a characteristic of the semiconductor device deteriorates due to a short circuit between the lower Cu wire and the pad metal 12 and destruction of the lower Cu wire or the circuit.
In order to solve the aforementioned problem, JP2004-235416A proposes a structure that a dummy wire is provided immediately under a pad metal so as to lessen influence due to cracking. However, such a structure has the following problems. The formation of the extra layer causes complication of processing. In addition, if the dummy wire is formed using an existing wiring layer, an area of an I/O region is disadvantageously enlarged, resulting in increase in chip size.